As serial links are required to operate at higher frequencies and over longer distances, more sophisticated mechanisms have been adopted to recover data from more severely degraded signals. However, conventional serial transceiver systems have shortcomings. For example, a conventional transmitter uses a conventional current mode-driver whose speed is limited to 0.43/RC due to a passive pull-up resistor. Furthermore, if a Delay-Locked Loop (DLL) is used in a transmitter, special consideration must be made in designing a wide-range multi-phase DLL due to a so-called stuck problem.
In a conventional receiver system that uses using oversampling, the receiver Phase-Locked Loop (PLL) is locked to a reference clock rather than to the transmitted signal. In a tracked two-times (2×) oversampling receiver, two samples are made per bit, one for the data sampling and the other for edge tracking. Prior art Two-times (2×) sampling pulses are illustrated in FIG. 1B. The sampled bits are examined to determine whether to move the sampling clock phase earlier (UP) or later (DOWN). In a prior art receiver that uses two-times (2×) sampling, the decision is binary: either UP or DOWN. FIG. 1C illustrates the prior art number of UP and DOWN pulses issues 90 by a phase adjustment circuitry from the jitter of FIGS. 1A and 1B.
When a two-times (2×) sampling system has reached a locked state, the number of UP pulses is equal to the number of DOWN pulses. Thus, the phase adjustment circuitry tends to oscillate when it is in a locked steady state. Furthermore, in such a 2× sampling system, the clock edge for data sampling could be quite off from the optimum center point as illustrated in FIG. 1A. This misplacement of the sampling clock is due to the asymmetric nature of severe jitter as illustrated by the histogram in FIG. 1B, and is not desirable.
Also, a conventional tracked three-times (3×) oversampling phase detector raises several design problems due to long pumping pulses persisting for one Voltage Controlled Oscillator (VCO) cycle time. (See Inyeol Lee, et al. “A 622 Mb/s CMOS Clock Recovery PLL with Time-Interleaved Phase Detector Array,” ISSCC Digest of Technical papers, pp. 198-199, February 1996.)
For better jitter performance, the Phase-Locked Loop should have a structure that is more immune to power-supply noise. The Phase-Locked Loop should also contain a smaller number of possible noise sources.
Conventional Voltage controlled Oscillators (VCOs) that use replica bias circuits are known to produce most of their jitter due to the noise in the bias voltage from the replica circuit (See Ian A. Young, et al., “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors,” IEEE JSSC, vol. 27, pp. 1599-1607, November 1992.) Due to these and other shortcomings of prior art transceiver systems, there is a need for an improved transceiver that provides robust clock and data recovery.